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| PRELIMINARY HM6C5332 HM6C5332 - 1.2GHz/250MHz Dual Frequency Synthesizer Features Description The HM6C5332 of full CMOS monolithic, dual frequency synthesizer is to be used as a local oscillator for RF and IF of a dual conversion transceiver. It is fabricated using Hyundai's standard CMOS process. HM6C5332 contains dual modulus prescalers. A 64/65 or a 128/129 prescaler can be selected for RF synthesizer and a 8/9 or 16/17 prescaler can be selected for IF synthesizer. Using digital phase locked loop technique, HM6C5332 provides the tuning voltage for voltage controlled oscillators to generate very stable low noise RF & IF local oscillator signals. Serial data is transferred into the HM6C5332 via three wire interface (Data, Enable, Clock). Supply voltage can range from 2.7 to 3.6 V. HM6C5332 features very low current consumption; 3.2mA at 3.0V. HM6C5332 is available in a 20-pin TSSOP package and 24-pin LGA (Leadless Grid Array) package Applications Functional Block Diagram Portable Wireless Communications Cordless and Cellular Telephone Systems Wireless Local Area Networks(WLANs) Cable TV Tuners(CATV) Other Wireless Communication Systems ! #$% Full CMOS RF frequency synthesizer Low Current Consumption Selectable Powersave Mode Dual Modulus Prescaler Selectable Charge Pump High Z State 2.7V to 3.6V Operation Small Out Line 20 Pin TSSOP Package 24 Pin LGA(Leadless Grid Array) Package fIN IF DO IF DO RF !" fIN RF PRELIMINARY Pin Assignment Leadless Grid Array Package Thin Shrink Small Outline Package TM Pin Description Pin No. HM6C5332 24-pin LGA Package Pin No. HM6C5332 20-pin TSSOP Package PIN NAME I/O Description 24 1 VDDRF - Power supply voltage input for RF analog and RF digital circuits. Input may range from 2.7V to 3.6V. VDDRF must equal VDDIF. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. Power Supply for RF charge pump. Must be VDDRF. Internal RF charge pump output. For connection to a loop filter for driving the input of an external VCO. Ground for RF digital circuitry. RF prescaler input. Small signal input from the VCO. This pin is to provide a bypass capacitor to the internal voltage supply and bypass capacitor must be placed between this pin and RF analog GND(Pin 7). With a slight performance degradation, this pin may be NC. Ground for RF analog circuitry. Oscillator input. The input has a VDDRF/2 input threshold and can be driven from an external CMOS or TTL logic gate. Ground for data interface, FoLD, and oscillator circuits. Multiplexed output of the RF/IF programmable or reference dividers, and RF/IF lock detect signals. CMOS output(See Programmable Modes) High impedance CMOS Clock input. Data for the various counters is clocked in on the rising edge, into the 22-bit shift register. Binary serial data input. Data entered MSB first. The last two bits are the control bits. High impedance CMOS input. Load enable high impedance CMOS input. When LE goes HIGH, data stored in the shift register is loaded into one of the 4 appropriate latches(control bit dependent). 2 3 4 5 6 7 8 10 11 12 14 2 3 4 5 6 7 8 9 10 11 12 VPPRF DoRF VSRFD finRF VIRF VSRFA OSCin VSS FoLD Clock Data O I I O I I 15 13 LE I PRELIMINARY Pin No. HM6C5332 24-pin LGA Package 16 17 Pin No. HM6C5332 20-pin TSSOP Package 14 15 PIN NAME VSIFA VIIF I/O Description - 18 19 20 22 23 16 17 18 19 20 finIF VSIFD DoIF VPPIF VDDIF I O - Ground for IF analog circuitry. This pin is to provide a bypass capacitor to the internal voltage supply and bypass capacitor must be placed between this pin and IF analog GND(Pin 14). With a slight performance degradation, this pin may be NC. IF prescaler input. Small signal input from the VCO. Ground for IF digital circuitry. Internal IF charge pump output. For connection to a loop filter for driving the input of an external VCO. Power Supply for IF charge pump. Must be VDDIF. Power supply voltage input for IF analog, IF digital, data interface, FoLD, and oscillator circuits. Input may range from 2.7V to 3.6V. VDDIF must equal VDDRF. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. No Connect 1,9,13,21 X NC - Block Diagram FoLD % "(* +,+ +,+ DoRF ( % & ' ) % & ' ) ( DoIF finRF ($$ ' !) ) ' finIF ) ! ) !"# ! # LE OSCin ! $ Data Clock ! $ $ ' !"# ! PRELIMINARY Absolute Maximum Ratings Power Supply Voltage VDD VPP Voltage on Any Pin with GND = 0V (VI) Storage Temperature Range (TS) Lead Temperature (solder 4 sec.) (TL) Thermal Resistance(Typical) JA (C/W) TSSOP Package 130C -0.3V to +4.2V -0.3V to +4.2V -0.3V to +4.2V -65C to +150C 260C Operating Conditions Power Supply Voltage VDD VPP Operating Temperature(TA) 2.7V to 3.6V VDD to 3.6V -40C to 85C CAUTION: Stress above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. Other conditions above those indicated in the operational sections of this specification are not implied. Electrical Characteristics Symbol Parameter VDD = 3.0V, -40C < TA < 85C, Except as Specified Conditions RF VDD=2.7V to 3.6V, f= 10KHz VDD=2.7V to 3.6V, f= 10KHz Min Typ 2.2 Max Units mA IDD IDD-PWDN fINRF fINIF fOSC f PfINRF PfINIF VOSC VIH VIL IIH IIL IIH IIL VOH VOL t CS t CH t CWH t CWL t ES t EW Power Supply Current IF Powerdown Current Operating Frequency Operating Frequency Oscillator Frequency. Maximum Phase Detector Freq. RF Input Sensitivity IF Input Sensitivity Oscillator Sensitivity High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Oscillator Input Current Oscillator Input Current High-Level Output Voltage Low-Level Output Voltage Data Clock Setup Time Data Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Clock to Load Enable Setup Time Load Enable Pulse Width 4.1 1.0 1 0.5 50 4 10 10 1.2 250 40 0 0 0.2 VDD 1.0 1.0 100 0.4 mA A GHz MHz MHz MHz dBm dBm VPP V V A A A A V VDD=3.0V VDD=2.7V to 3.6V VDD=2.7V to 3.6V OSCIN * * VIH =VDD=3.6V* VIL =0V, VDD=3.6V* VIH =VDD=3.6V VIL =0V, VDD=3.6V IOH = -500 A IOL = 500 A See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing -10 -10 0.5 0.8 VDD -1.0 -1.0 -100 VDD-0.4 50 10 50 50 50 50 V ns - * Clock, Data and LE. Does not include fINRF, fINIF and OSCIN. PRELIMINARY Functional Description The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and the 15-bit and 18-bit N Counters (intermediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA input, MSB first. The last two bits are the Control Bits. The DATA is transferred into the counters as follows: CONTROL BITS C1 C2 0 0 0 1 1 0 1 1 DO IF DATA LOCATION IF R Counter RF R Counter IF N Counter RF N Counter fIN IF ! #$% !" DO RF fIN RF Programmable Reference Dividers (IF and RF R Counters) If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22bit shift register into a latch which sets the 15-bit R Counter. Serial data format is shown below. 15-Bit Programmable Reference Divider Ratio (R Counter) DIVIDE RATIO 3 4 * R 15 0 0 * R 14 0 0 * R 13 0 0 * R 12 0 0 * R 11 0 0 * R 10 0 0 * R 9 0 0 * R 8 0 0 * R 7 0 0 * R 6 0 0 * R 5 0 0 * R 4 0 0 * R 3 0 1 * R 2 1 0 * R 1 1 0 * 32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTES: 1. Divide ratios less than 3 are prohibited. 2. Divide ratio: 3 to 32767. 3. R1 to R15: These bits select the divide ratio of the programmable reference divider. 4. Data is shifted in MSB first. PRELIMINARY Programmable Divide (N Counter) The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4bit or 7-bit latch (which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data format is shown below. For the IF N counter bits 5, 6, and 7 are don't care bits. The RF N counter does not have don't care bits. !"#$!% 7-Bit Swallow Counter Divide Ratio (A Counter) RF DIVIDE RATIO A 0 1 * IF N 4 0 0 * N 7 0 0 * N 6 0 0 * N 5 0 0 * N 3 0 0 * N 2 0 0 * N 1 0 1 * DIVIDE RATIO A 0 1 * N 7 X X * N 6 X X * N 5 X X * N 4 0 0 * N 3 0 0 * N 2 0 0 * N 1 0 1 * 127 1 1 1 1 1 1 1 15 X X X 1 1 1 1 NOTES: 1. Divide ratio 0 to 127 2. B A X = Don't care condition 11-Bit Programmable Counter Divide Ratio (B Counter) DIVIDE RATIO A 3 4 * N 18 0 0 * N 17 0 0 * N 16 0 0 * N 15 0 0 * N 14 0 0 * N 13 0 0 * N 12 0 0 * N 11 0 0 * N 10 0 1 * N 9 1 0 * N 8 1 0 * 2047 1 1 1 1 1 1 1 1 1 1 1 NOTES: 1. Divide ratio 3 to 2047 (divide ratios less than 3 are prohibited). 2. B A Pulse Swallow Function fVCO = [(P B) + A] fOSC/R fVCO: Output frequency of external voltage controlled oscillator (VCO) B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047) A: Preset divide ratio of binary 7-bit swallow counter (0A127 {RF}, 0A15 {IF}, AB) fOSC: Output frequency of the external reference frequency oscillator R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767) P: Preset modulus of dual modulus prescaler (for IF: P=8 or 16; for RF: P=64 or 128) PRELIMINARY Programmable Modes Several modes of operation can be programmed with bits R16-R18 including the phase detector polarity and charge pump High Z State. The prescaler and powerdown modes are selected with bits N19 and N20. The programmable modes and truth table for the programmable modes are shown below. C1 0 0 1 1 C2 0 1 0 1 R16 IF Phase Detector Polarity RF Phase Detector Polarity R17 IF ICPO RF ICPO R18 IF DO High Z RF DO High Z R19 IF LD RF LD IF Prescaler RF Prescaler R20 IF FO RF FO Powerdown IF Powerdown RF Mode Select Truth Table PHASE DETECTOR POLARITY 0 1 Negative Positive DO High Z STATE Normal Operation High Z State ICPO (NOTE 1) LOW HIGH IF PRESCALER 8/9 16/17 RF PRESCALER 64/65 128/129 POWERDOWN (NOTE 2) Powered Up Powered Down NOTES: 1. Activation of the IF PLL or RF PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective fIN inputs (to a high impedance state). Powerdown forces the respective charge pump and phase comparator logic to a High Z State condition. The R counter functionality does not become disabled until both IF and RF powerdown bits are activated. The OSCIN pin reverts to a high impedance state when this condition exists. The control register remains active and capable of loading and latching in data during all the powerdown modes. FO LD (Pin 10) Output Truth Table RF R[19] (RF LD) 0 0 1 1 X X X X 0 0 1 1 IF R[19] (IF LD) 0 1 0 1 0 0 1 1 0 1 0 1 RF R[20] (RF FO) 0 0 0 0 0 1 0 1 1 1 1 1 IF R[20] (IF FO) 0 0 0 0 1 0 1 0 1 1 1 1 FO OUTPUT STATE Disabled (Note1) IF Lock Detect (Note2) RF Lock Detect (Note2) RF/IF Lock Detect (Note2) IF Reference Divider Output RF Reference Divider Output IF Programmable Divider Output RF Programmable Divider Output For Internal Use Only For Internal Use Only For Internal Use Only Counter Reset (Note4) X = don't care condition NOTES: 1. When the FO LD output is disabled, it is actively pulled to a low logic state. 2. Lock detect output provided to indicate when the VCO frequency is in "lock". When the loop is locked and a lock detect mode is selected, the pins output is HIGH, with narrow pulse LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked. 3. The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits then N counter resumes counting in "close" alignment with the R counter. (The maximum error is one prescaler cycle). If the Reset bits are activated the R counter is also forced to Reset, allowing smooth acquisition upon powering up. PRELIMINARY Phase Detector Polarity Depending upon VCO characteristics, R16 bit should be set accordingly: When VCO characteristics are positive like (1), R16 should be set HIGH; When VCO characteristics are negative like (2), R16 should be set LOW. Serial Data Input Timing &'& ,-. ,-. ()* (+ ) (+ NOTES: 1. Parenthesis data indicates programmable reference divider data. 2. Data shifted into register on clock rising edge. 3. Data is shifted in MSB first. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VDD/2. The test waveform has an edge rate of 0.6V/ns with amplitudes of 2.2V at VDD = 2.7V and 2.6V at VDD = 3.6V. ,(-. ,(-. Phase Comparator and Internal Charge Pump Characteristics " " ( "/" "0" "1" "1" "1" NOTES: 1. Phase difference detection range: -2to +2 2. The minimum width pump up and pump down current pulse occur at the DO pin when the loop is locked. 3. R16 = HIGH PRELIMINARY Powerdown Operation Synchronous and asynchronous powerdown modes are both available. Synchronously powerdown occurs if the respective loop's R18 bit (Do High Z State) is LOW when its N20 bit (Powerdown) becomes HI. Asynchronous powerdown occurs if the loop's R18 bit is HI when its N20 bit becomes HI. In the synchronous powerdown mode, the powerdown function is gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program bit N20 is loaded, the part will go into powerdown mode when the charge pump reaches a High Z condition. In the asynchronous powerdown mode, the device powers down immediately after the LE pin latches in a HI condition on the powerdown bit N20. Activation of either the IF or RF PLL powerdown conditions in either synchronous or asynchronous modes forces the respective loop's R and N dividers to their load state condition and debiasing of its respective fin input to a high impedance state. The oscillator circuitry function does not become disabled until both IF and RF powerdown bits are activated. The control register remains active and capable of loading and latching data during all of the powerdown modes. The device returns to an actively powered up condition in either synchronous or asynchronous modes immediately upon LE latching LOW data into bit N20. Powerdown Mode Select Table R18 0 1 0 1 N20 0 0 1 1 Powerdown Status PLL Active PLL Active (Charge Pump High Z State) Synchronous Powerdown Initiated Asynchronous Powerdown Initiated Physical Dimensions (unit : ) Leadless Grid Array Package PRELIMINARY Physical Dimensions continued (unit : ) Thin Shrink Small Outline Package |
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